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authorCayetano Santos <[email protected]>2024-10-29 09:55:46 +0100
committerLudovic Courtès <[email protected]>2025-01-07 18:04:57 +0100
commit952a179f4415823efbae3fa7d8d49f5fb878c89e (patch)
treef689afe147d19443081033e889c5305fb6f8257b
parent3b31ef750affe3a5dcb82437647cb98f607648a2 (diff)
gnu: Add yosys-clang.
* gnu/packages/fpga.scm (yosys-clang): New variable. Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da Signed-off-by: Ludovic Courtès <[email protected]>
-rw-r--r--gnu/packages/fpga.scm20
1 files changed, 20 insertions, 0 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index df0652ae44..8e3ee00122 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -239,6 +239,26 @@ For synthesis, the compiler generates netlists in the desired format.")
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
+(define-public yosys-clang
+ (package
+ (inherit yosys)
+ (name "yosys-clang")
+ (arguments
+ (substitute-keyword-arguments (package-arguments yosys)
+ ((#:make-flags _ #f)
+ #~(list "CC=clang"
+ "CXX=clang++"
+ (string-append "PREFIX=" #$output)))
+ ((#:phases phases)
+ #~(modify-phases #$phases
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-clang" make-flags)))))))
+ (inputs
+ (modify-inputs (package-inputs yosys)
+ (append clang)))
+ (synopsis "FPGA Verilog RTL synthesizer (Clang variant)")))
+
(define-public icestorm
(let ((commit "2bc541743ada3542c6da36a50e66303b9cbd2059")
(revision "4"))