diff options
| author | Cayetano Santos <[email protected]> | 2024-11-09 20:08:24 +0100 |
|---|---|---|
| committer | Maxim Cournoyer <[email protected]> | 2024-11-12 17:41:38 +0900 |
| commit | 66b1471199cc077feb39ae58d5365e03f71f8fdb (patch) | |
| tree | a2822d1d5c6a6dc3e83c95fbdefa04b2b7da941a /gnu | |
| parent | 742765656e3f58f396915e2291ded0f12aa6b9a1 (diff) | |
gnu: iverilog: Re-add zlib to inputs.
Fixes issue introduced in
<https://git.savannah.gnu.org/cgit/guix.git/commit/?id=b32f8bc9da> which
removed zlib. This caused failures in the yosys test suite.
* gnu/packages/fpga.scm (iverilog) [inputs]: Add zlib.
Change-Id: I262db5db43527a3a2a1753163f7b9a4104f7e895
Signed-off-by: Maxim Cournoyer <[email protected]>
Diffstat (limited to 'gnu')
| -rw-r--r-- | gnu/packages/fpga.scm | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index c658ed8da4..ecf111f8be 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -124,6 +124,7 @@ formal verification.") #:make-flags #~(list (string-append "PREFIX=" #$output)) #:bootstrap-scripts #~(list "autoconf.sh"))) (native-inputs (list autoconf bison flex gperf)) + (inputs (list zlib)) (home-page "https://steveicarus.github.io/iverilog") (synopsis "FPGA Verilog simulation and synthesis tool") (description |